Field
Embodiments described herein relate to semiconductor packaging. More particularly embodiments relate to fan out system in packages (SiPs).
Background Information
The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. As a result, various multiple-die packaging solutions such as system in package (SiP) and package on package (PoP) have become more popular to meet the demand for higher component density devices.
System in package (SiP) structures typically include two or more dissimilar die in a single package as a functional system or sub-system. For example, logic and memory may be combined into a single package, along with other components such as passive devices, MEMS devices, sensors, etc. The die within a SiP can be stacked vertically or arranged horizontally on a carrier. The die are commonly connected with off-chip wire bonds or solder bumps. A SiP may be assembled on an interposer to fan out electrical terminals for an integrated product.
More recently, package on package (PoP) structures have become increasingly popular. PoP technology generally involves the installation of two or more packages on top of each other with a standard interface to rout signals between them. High component density devices may commonly have a memory package installed on top of a logic package or system on chip (SoC) package. Common PoP structures include an interposer between the top and bottom packages to fan out electrical terminals.